Mixed Gates: Leakage Reduction techniques applied to Switches for on-chip Networks

The power dissipation due to leakage currents increases dramatically and endangers various aspects of current and future integrated circuits. However, the issue is recognized and several proposals have already been made to cope with this. Unfortunately, leakage reduction is often traded off for performance. Therefore, an enhanced Dual Vth / Dual Tox CMOS approach is presented, which achieves an average leakage reduction of roughly 83 % without any drawback on performance compared to a standard approach. This corresponds to an additional reduction of 10 % compared to a Dual Vth / Dual Tox CMOS approach. The paper introduces the used transistor and gate types before a testbench of switches for a network-on-chip and the achieved results are presented and discussed.